Latest #risc Threads 
Commercial out-of-order RISC-V cores turn out to be vulnerable to the major Spectre variants, and most of the mitigations that exist on x...
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In this blog I will look at some of the drivers for the growth of RISC-V, its value proposition and explain why supporting RISC-V is impo...
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ESP32-S31 delivers comprehensive multi-protocol connectivity, rich multimedia interfaces, and hardware-accelerated security for next-gene...
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This Buildroot-based basic Linux distribution runs natively on the RP2350’s Hazard3 RISC-V cores — albeit not very quickly.
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How I enabled the PowerVR GPU on the TH1520 SoC by writing the missing kernel drivers.
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At RISC-V Summit North America 2025, Andrea Gallo, CEO RISC-V International, and Phil Wennblom, Chair of the ISO/IEC Joint Technical Comm...
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Once a hyperscaler or a cloud builder gets big enough, it can afford to design custom compute engines that more precisely match its needs...
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Some high-performance RISC-V processors are in the pipeline for the rest of the year 2025, namely UltraRISC UR-DP1000, Zhihe A210, and Sp...
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Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC...
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This Week's Trending
Commercial out-of-order RISC-V cores turn out to be vulnerable to the major Spectre variants, and most of the mitigations that exist on x...
New
This Month's Trending
This Year's Trending
Once a hyperscaler or a cloud builder gets big enough, it can afford to design custom compute engines that more precisely match its needs...
New
ESP32-S31 delivers comprehensive multi-protocol connectivity, rich multimedia interfaces, and hardware-accelerated security for next-gene...
New
At RISC-V Summit North America 2025, Andrea Gallo, CEO RISC-V International, and Phil Wennblom, Chair of the ISO/IEC Joint Technical Comm...
New
This Buildroot-based basic Linux distribution runs natively on the RP2350’s Hazard3 RISC-V cores — albeit not very quickly.
New
How I enabled the PowerVR GPU on the TH1520 SoC by writing the missing kernel drivers.
New
New
In this blog I will look at some of the drivers for the growth of RISC-V, its value proposition and explain why supporting RISC-V is impo...
New
Last Three Year's Trending
TCC RISC-V Compiler runs in the Web Browser (thanks to Zig Compiler).
Today we’re running Apache NuttX RTOS inside a Web Browser. What i...
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A new Rocky Linux blog post/announcement has been posted!
Get the full details here: https://rockylinux.org/news/rockylinux-support-for...
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Some high-performance RISC-V processors are in the pipeline for the rest of the year 2025, namely UltraRISC UR-DP1000, Zhihe A210, and Sp...
New
A new CentOS blog post/announcement has been posted!
Get the full details here: Initial CentOS Support for RISC-V – Blog.CentOS.org
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Get Started with Embedded Swift on ARM and RISC-V Microcontrollers.
We’re pleased to introduce a repository of example projects that dem...
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Milk-V Goes After the Raspberry Pi Compute Module 4 with a Pin-Compatible RISC-V Alternative.
The Milk-V Mars Compute Module includes du...
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Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC...
New
A new CentOS blog post/announcement has been posted!
Get the full details here: CentOS for RISC-V Now Available – Blog.CentOS.org
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Lichee Console 4A is a $299 mini-laptop with a RISC-V processor and 7 inch display - Liliputing.
Lichee Console 4A is a $299 mini-laptop...
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Android and RISC-V: What you need to know to be ready.
You can build, test, and run the Android support for RISC-V on your own machine.
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RISC-V battles to get messaging right over open standard.
It’s the difference between export limits on specific chips – and a problemati...
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VPR: Nordic’s First RISC-V Processor.
VPR (pronounced “Viper”) is Nordic Semiconductor’s first RISC-V processor, landing in the new nRF5...
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With soldered RAM and eMMC storage, this is not "a consumer-ready experience."
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Introducing a new RISC-V Mainboard from DeepComputing.
We’re excited to share a preview of a Framework Laptop 13 Mainboard with a new CP...
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Trending Over Three Years
Writing an OS in Rust to run on RISC-V.
Writing an OS in Rust to run on RISC-V. GitHub Gist: instantly share code, notes, and snippets.
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Processor
• SiFive U74 RISC-V Dual core with 2MB L2 cache @ 1.5GHz
• Vision DSP Tensilica-VP6 for computing vision
• NVDLA Engine (conf...
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Report: Apple to Move a Part of its Embedded Cores to RISC-V, Stepping Away from Arm ISA.
According to Dylan Patel of SemiAnalysis sourc...
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Just watching now, seems well researched - very interesting actually…
He’s a Windows user btw :upside_down_face:
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The Genius of RISC-V Microprocessors.
How the instruction set for RISC-V processors has been designed cleverly for both simplicity and h...
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October update: An Ox, no bull | PINE64.
I hope that the good news and all the announcements of this month will make up for the much del...
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RISC-V Linux on ESP32.
I’ve been playing with the idea of running linux on ESP32 since the first days I’ve met its more robust module, t...
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The first RISC-V portable computer is now available.
The DevTerm R-01 is a RISC-V based “slabtop” computer.
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The RISC Deprogrammer.
I should write up a larger technical document on this, but in the meanwhile is this short (-ish) blogpost. Everyt...
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RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures.
Most modern CPU architectures are based on the von Neumann principle, w...
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The joint venture will first target automotive, with IoT and mobile coming later.
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Designing a RISC-V CPU, Part 1: Learning hardware design as a software engineer
Tue 16 February 2021
I have no experience in digital log...
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selfie.
An educational software system of a tiny self-compiling C compiler, a tiny self-executing RISC-V emulator, and a tiny self-hosti...
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GitHub - OpenXiangShan/XiangShan: Open-source high-performance RISC-V processor.
Open-source high-performance RISC-V processor. Contribu...
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NASA Selects SiFive and Makes RISC-V the Go-to Ecosystem for Future Space Missions - SiFive.
SiFive X280 delivers 100x increase in compu...
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